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pj3843b high performance current mode controller 1-15 2002/01.ver.a he pj3843b series is high perform ance fixed frequen cy current mode controllers. this is specifically designed fo r off-line and dc-to-dc convert er applications o ffering the designer a cost effective solution with minimal external components.this integrated circuits featu re a tr immed oscillator for precise duty cycle control, a temperature compensated r e feren ce, high gain er ror amplifie r, curr ent sensing comparator,and a high current totem pole output ideally suited for driving a power mosfet. also included are protective features consisting of input and referen ce undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting , programmable output deadtime, and a latch for single pulse metering. this device is available in 8-pin dual-in-line plastic packag es as well as the 8 -pin plastic surface mount (sop-8). the sop-8 package has separate power and ground pins fo r the totem pole output stage. the pj3843b is tailored for lower voltage applications havinguvlo thresholds of 8.5v(on) and 7.6v(o ff). trimmed oscillator discharge current for precise duty cycle control current mode operation to 500khz automatic feed forward compensation latching pwm for cycle-by-cycl e current limiting internally trimmed reference with undervoltage lockout high current totem pole output input undervoltage lockout with hystersis low start-up and operating current device operating temperature packag e PJ3843BCD dip-8 pj3843bcs sop-8 the document contains information on a new product.specifications and information herein are subject to change without notice. t dip-8 sop-8 simplified block diagra m pin numbers adjacent to terminals are for the 8-pin dual-in-line packag e. pin numbers in parenthesis are fo r the sop-8 package. features p in: 1. compensation 5 . gnd 2. voltage feedback 6. output 3. current sense 7. vcc 4. r t /c t 8. vref ordering info rmation -20 to +85 0 c
pj3843b high performance current mode controller 2-15 2002/01.ver.a rating symbol value unit total power supply and zener current (i cc +i z ) 30 ma output current source or sink (note 1) io 1.0 a output energy (capacitive load per cycle) w 5.0 j current sense and voltage feedback inputs vin -0.3 to +5.5 v error amp output sink current io 10 ma power dissipation and thermal characteristics plastic dip maximum power dissipation @ t a =25 thermal resistance junction to air plastic dip maximum power dissipation @ t a =25 thermal resistance junction to air p d r ja p d r ja 862 145 1.25 100 mw /w w /w operating junction temperature t j +150 operatu re ambient t emperature t a 0 to +70 storage temperature range tstg -65 to +150 pj3843b characteristic symbol min typ max unit reference section reference output voltage (io=1.0ma,t j = 25 ) vref 4.9 5.0 5.1 v line regulation (v cc =12v to 25v) regline - 2.0 20 mv load regulation (io =1.0ma to 20ma) regload - 3.0 25 mv temperature stability ts - 0.2 - mv/ total output variation over line,load ,and temperature vref 4.82 - 5.18 v output noise voltage (f = 10hz to 10khz, t j =25 ) vn - 50 - v long term stab ility ( t a =125. for 1000 hours) s - 5.0 - mv output short circuit current isc -30 -85 180 ma oscillator section frequency t j =25 t a =t low to t high fo s c 47 46 52 - 57 60 khz frequency change with voltage (v cc =12v to 25v) fo s c/ v - 0.2 1.0 % frequency change with temperature t a =t low to t high fo s c/ t - 5.0 - % oscillator voltage swing ( peak-to-peak) vosc - 1.6 - v discharg e current (vosc=2.0v) t j =25 t a =t low to t high idischg 7.5 7.2 8.4 - 9.3 9.5 ma note: 1. maximum package power dissipation limits must be observed. 2. adjust v cc above the start-up threshold befo re se tting to 15v. 3. low duty cycle pulse technique are used during test to maintain junction temperature as close to ambient as possibl e. t low = 0 t high = + 70 4. this parameter is measured at the latch trip point with v fb = 0v. v output compensation 5. comparator gain is defined as : av = v current sense input m aximum ratin g electrical characteristics (v cc = 15v (note 2), r t =10k, c t =3.3nf, t a = t low to t high (note 3) unless otherwise noted)
pj3843b high performance current mode controller 3-15 2002/01.ver.a pj3843b characteristic symbol min typ max unit error amplifier section voltage feedback input (vo=2.5v) v fb 2.42 2.5 2.58 v input bias current (v fb =5.0v) i ib - -0.1 -2.0 ? open-loop voltage gain (vo=2.0v to 4.0v) a vol 65 90 - db unity gain bandwidth (t j =25 ) bw 0.7 1.0 - mhz power supply rejection radio (v cc =12v to 25v) psrr 60 70 - db output current sink (vo=1.1v, v fb =2.7v) source ( vo=5.0v, v fb =2.3v) i sink i source 2.0 -0.5 12 -1.0 - - ma output voltage swing high state (r l =15k to ground, v fb =2.3v) v oh 5.0 6.2 - v low state (r l =15k to vref, v fb =2.7v) v ol - 0.8 1.1 current sense section current sense input voltage gain (note 4&5) av 2.85 3.0 3.15 v/v maximum current sense input threshold(note 4) v th 0.9 1.0 1.1 v power supply rejection radio v cc =12v to 25v,note 4 p srr - 70 - db input bias current i ib - -2.0 -10 ? propagation delay(current sense input to output) t plh(in/out) - 150 300 ns output section output voltage low state (isink=20ma) (isink=200ma) high state (isource=20ma) (isource=200ma) v ol v oh - - 13 12 0.1 1.6 13.5 13.4 0.4 2.2 - - v output voltage with uvlo activated v cc =6.0v,isink=1.0ma v ol (uvlo) - 0.1 1.1 v output voltage rise time (c l =1.0nf,t j =25 ) tr - 50 150 ns output voltage fall time (c l =1.0nf,t j =25 ) tf - 50 150 ns undervoltage lockout section start-up threshold vth 7.8 8.4 9.0 v minimum operating voltage after turn-on v cc(min) 7.0 7.6 8.2 v pwm section duty cycle maximum minimum dcmax dcmin 94 - 96 - - 0 % total device power supply current start-up, v cc =6.5v operating (note 2) i cc - - 0.25 12 0.5 17 ma power supply zener voltage (i cc =25ma) vz 30 36 - v e lectrical charact eristics (v cc =15v ( note 2 ) , r t =10 k c t =3.3nf t a =t lo w to t high ( note 3 ) unless otherwise
pj3843b high performance current mode controller 4-15 2002/01.ver.a figure 1- output dead time versus oscillator freq uency figure 2- timing resistor versus oscillator freq uency figure 3-oscillator discharge current versus temperature figure 4-maximu m output duty cycle versus timing resistor figure 5-error amp small signal figure 6-error amp large signal transient response transient response
pj3843b high performance current mode controller 5-15 2002/01.ver.a figure 7-error amp open-loop gain and phase versus freq uency figure 8-current sense input threshold versus error amp output voltage figure 9-reference voltage change versus source current figure 10-reference short circuit current versus temperature figure 11- reference load regulation figure 12-reference line regulation
pj3843b high performance current mode controller 6-15 2002/01.ver.a figure 13-output saturation voltage versus load current figure 14-output waveform figure 15-output cross conduction figure 16-supply current versus supply voltage
pj3843b high performance current mode controller 7-15 2002/01.ver.a figure 17-representative block diagram pin numbers adjacent to terminals are for the 8 pin dual-in-line package. pin numbers in parenthesis are for the sop-14 package. figure 18-timing diagram two undervoltage lockout comparators have been incorporat ed to guarantee that the ic is fully functional before the output stage is enabled. the positive power supply terminal (v cc ) and the refe ren ce output (vref) are ea ch monitored by separate comparators.each has built-in hysteresis to prevent erratic output behavior as their respe ctive thresholds are crossed.t he v cc comparator upper and lower thresholds are 8.4 v/7.6 v for the uc3843b the vref comparator upper and lower thresholds are 3.6v/3.4v.the large hysteresis and low start-up current o f the uc3843 makes it ideally suited in off-line conv erter applications where effi cient bootstrap start-up technique (figure 33).a 36 v zener is connected as a shunt regulator from v cc to ground.its purpose is to protect the ic from excessive voltage that can occur during system start-up. the minimum operating voltage 8.2 v for the uc3843b undervoltage lockout
pj3843b high performance current mode controller 8-15 2002/01.ver.a output these devices contain a single totem pole output stage that was specifically designed for direct drive of power mosfet ? s. it is capable o f up to 1.0a peak drive curr ent and has a typical rise and fall time of 50 ns with a 1.0nf load. additional internal circuitry has been added to keep the output in a sinking mode whenever an undervoltage lockout is active.this characteristic eliminates the need for an external pull-down resistor. the sop-8 surface mount package provides separate pins fo r vc(output supply) and power ground.proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. this becomes particularly useful when redu cing the ipk(max ) clamp level.the separat e vc supply input allows the designer added fi exlbility in tailoring the drive voltage independent of vcc.a zen er clamp is typically connected to this input when driving power mosfet s in systems where vc c is greate r than 20v. figure 25 shows proper power and control ground connections in a current sensing power mosfet application. ref erenc e the 5.0v bandgap reference is tr immed to2.0% on the uc3843b.its promary purpose to supply charging current to the oscillator timing capacitor.the reference has short circuit protection and is capable of providing in excess of 20ma for powering additional control system circuitry. design considerations do not attempt to construct the converter on wirew rap or plug-in prototype boards. high frequen cy circuit layout techniques are imperative to prevent pulsewidth jitter.this is usually caused by excessive noise pick-up imposed on the current sense or voltage feedb ack inputs.noise immunity can be improved by lowering circuit impedances at these points.the printed circuit layout should contain a ground plane with lowcurrent signal and high-current switch and output grounds returning separate paths back to the input filter capacitor.ceramic bypass cap acitors(0.1 f) connect ed directly to vcc,vc, and vref may b e required depending upon circuit layout . this provides a low impedance path fo r filtering the high frequency noised. all high current l oops should be kept as short as possible using heavy copper runs to minimize radiated emi. t he error amp compensation circuitry and the converter output voltage divider should b e located close to the ic and as far as possible from the power switch and other noise generating components. figure 19-continuous current wavefroms current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current,this instab ility is independent of the regulators closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequ ency and peak current detecting. figure 19a shows the phenomenon graphically, at t 0 , switch conduction begins , causing the inductor current to rise at a slope of m 1 . t his slope is a function of the input voltage divided by the inductance. at t1, the current sense input r each es the threshold established by the control voltage. this causes the switch to turn off and the curr ent to decay at a slope of m 2 , until the next oscillator cycle. this unstable c ondition can be shown if a perturbation is added to the control voltage , resulting in a small l (dashed line). with a fixed oscillator period, the current decay time is reduced, and the minimum curr ent at switch turn-on(t 2 ) is increased by l+ l m 2 /m 1 . t he minimum current at the next cycl e (t 3 ) decr eases to ( l+ l m 2 /m 1 )(m 2 /m 1 ). this perturbation is multiplied by m 2 /m 1 on each succ eeding cy cle , alternat ely incre asing and decreasing the inductor current at switch turn-on, several oscillator cycles may be required before the i nductor current rea ches ze ro causing the process to commence ag ain. if m 2 /m 1 is greater than 1, the converter w ill be unstable . figure 19b shows that by adding an artificial ramp that is synchronized with the pwm clock to the control voltage . the l perturbation will decrease to zero on su cceeding cycles. t his compensating ramp (m 3 ) must have a slope equal to or slightly greater than m 2 /2 for stability . with m 2 /2 slope compensation , the average inductor current follows the control voltage yielding true current mode operation. the compensating ramp can be derived from the oscillator and added to either the voltage feedb ack or current sense inputs (figure 32).
pj3843b high performance current mode controller 9-15 2002/01.ver.a figure 20-external clock synchroni zation figure 21-external duty cycle clamp and multi unit synchroni zation the diode clamp is required if the sync amplitude is large enough to the cause the bottom side of c t to go more than 300mv below g rou nd . figure 22-adjustable reduction of clamp level 1.44 r b f= d max = (r a +r b ) r a +2r b figure 23-soft-start circuit figure 24-adjustable buffered reduction of clamp level with soft-star i soft-start =3600c in f figure 25-current sensing power mosfet virtually lossless current sensing can be achieved with the implementation of a sensefet power switch.for proper operation during over current conditions.a reduction of the ipk(max) clamp level must be implemented.refer to figure 22 and 24.
pj3843b high performance current mode controller 10-15 2002/01.ver.a figure 26-current waveform spike suppression figure 27-mosfet parasitic oscillations the addition of rc filter will eliminate instability caused by the leading edge splik on the current waveform. figure 28-bipolar transistor drive figure 29-isolated mosfet drive the totem-pole output can furnish negative base current for enhanced transistor turn-off,with the additions of capacitor c1. figure 30-latched shutdown figure 31-error amplifier compensation the mcr101 scr must be selected for a holding of less than 0.5ma at t a (min).the simple two transistor circuit can be used in place of the scr as shown.all resistors are 10k. error am p com pensation circuit for stabilizing any currentm ode t opology except for boost and fly back converters operating with continuous inductor current. error am p com pensation circuit for stabilizing any currentm ode t opology except for boost and fly back converters operating with continuous inductor current.
pj3843b high performance current mode controller 11-15 2002/01.ver.a figure 32-slope com pensation the buffered oscillator ramp can resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. figure 33-27 w att off-line regulation t 1-primary:45 t urns #26 awg secondary 12v :9 turns #30 awg (2 strands ) bif iliar w ound l1-15 h at 5.0a, coilcraft 27156. secondary 5.0v: 4 turns (six strands) #26 hexf iliar w ound l2.l3-25 h at 1.0a, coilcraft 27157. secondary feedback : 10 turns #30 awg (2 strands) bif iliar w ound core: ferroxcube ec35-3c8 bobbin : ferroxcube ec35pcb1 gap : 0.10? for a primary inductance o f 1.0mh line regulation:5.0v 12v vin=95 to 130 vac =50mv or 0.5% =24mv or 0.1% load regulation: 5.0v 12v vin=115vac, iout =1.0a to 4.0a vin=115vac,iout=100ma to 300ma =300mv or 3.0% =60mv or 0.25% output ripple: 5.0v 12v vin=115vac 40mvp-p 80 vp-p efficien cy vin=115vac 70% all outputs are at nominal load currents unless otherwise noted.
pj3843b high performance current mode controller 12-15 2002/01.ver.a figure 21-33 watt off-line flyback converter with soft-start and primary power limiting t1 coilcraft 11-464-16, 0.025? gap in each leg baobbin : coilcraft 37-573 windings: primary , 2 each: 75 turns #26 awg bifilar wound feedback: 15 turns #26 awg secondary , 5.0v: 6 turns #22 awg bifiar wound secondary , 5.0v: 14 turns #24 awg bifiar wound l1 coilcraft z7156. 15 f @ 5.0a l2,l3 coilcraft z7157. 25 f @ 1.0a test conditions results line regulation 5.0v vin=95 to 135 vac, io=3.0a 20mv 0.40% line regulation 12v vin=95 to 135 vac, io=0.75a 52mv 0.26% line regulation 5.0v vin=115 vac, io=1.0 to 4.0a 476mv 9.5% line regulation 12v vin=115 vac, io=0.4 to 0.9a 300mv 2.5% line regulation 5.0v vin=115 vac, io=3.0a 45 mvp-p p.a.r.d. line regulation 12v vin=115 vac, io=0.75a 75 mv p-p p.a.r.d. efficien cy vin=115 vac, io 5.0v=3.0a io 12=0.75a 74%
pj3843b high performance current mode controller 13-15 2002/01.ver.a pin function description pin no. function description 8-pin 1 2 3 4 5 6 7 8 compensation voltage feedback current sense r t /c t gnd output vcc vref this pin is the error amplifier output and is made available fo r loop compensation this is the inverting input of the error ampli fier. it is normally connect ed to the switching power supply output through a resistor divider. a voltage proportional to inductor current is connected to this input. the pwm uses this information to terminate the output switch conduction. the oscillator frequency and maximum output duty are programmed by connecting resistor r t to vref and capacitor c t to ground operation to 500khz is possible. this pin is the combined control circuitry and power ground (8-pin packag e only). this output directly drives the gate of a power mosfet.peak current up to 1.0a are soured and sunk by this pin. this pin is the positive supply of the control ic. this pin is the reference output . it provides charging current fo r capa citor c t through resistor r t .
pj3843b high performance current mode controller 14-15 2002/01.ver.a operating description the uc3843b series are high performan ce, fixed frequency, current mode controllers, they are speci fically designed for o ff-l ine and dc-to-dc converter applications offering the designer a cost effective solution with minimal external components . a representative block diagram is shown in figure 17. oscillator the oscillator frequency is programmed by the values selected for the timing com ponents r t and c t . capacitor c t is charged from the 5.0v reference through resistor r t to approximately 2.8v and discharge to 1.2v by an internal current sink.during the discharge o f c t , the oscillator generat es an internal blanking pulse that holds the center i nput o f the nor gate high. this causes the output to be in a low state, thus producing a controlled amount of output dead time. figure 1 shows r t versus oscillator frequency and figure 2, output deadtime versus frequency, both for given values of c t . note that many values of r t and c t will give the same oscillator frequency but only onne combination w ill yield a specific output deadtime at a given frequency. the oscillator thresholds are temperature compensat ed, and the discharge current is trimmed and guaranteed to within 10% at t j =25 . these internal circuit refinements minimum variations of oscillator frequency and maximum output duty cycle. the results are shown in figure 3 and 4. in many noise sensitive applications it may be desirable to frequency-lock the c onverter to an extern al system clock. this can be accomplished by applying a clock signal to the circuit shown in figure 20. for reliable locking. t he fre e-r unning osc illator frequ ency should be set about 10% less than the clock frequency . a method for mu lti unit synchronization is shown in figure 21. by tailoring the clock wave form, accu rate output duty cycle clamping can be achiev ed. error amplifier a fully compensated error ampli fier with access to the inverting input and output is provided. it features a typical dc voltage gain of 90db, and a unity gain bandwidth of 1.0mhz with 57 degrees o f phas e margin (figure 7). the non-inverting input is internally biased at 2.5v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input. the maximum input bias current is -2.0 a which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. the error amp output (pin 1) is provided for ext ernal loop compens ation (figure 31). the output voltage is offs et by two diode drops ( 1.4v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that no drive pulses appear at the output(pin 6) when pin 1 is at its lowest state (v ol ). this occurs when the power supply is operating and the load is removed, or at the beginning of a soft-start interval (figure 23,24). the error amp minimum feedback resistance is limited by the amplifier's source current (0.5ma) and the required output voltage (v oh ) to reach the comparato r? s 1.0v clamp level: r f(min) = [3.0 (1.0v)+1.4v] / 0.5ma = 8800 ? current sense comparator and pwm latch the uc3843b operate as a current mode controller, whereby output switch conduction is initiated by the osc illator and terminated when the peak inductor current reaches the threshold level established by the error ampli fier output/compensation (pin 1). thus the erro r signal controls the peak inducto r current on a cy cle-by -cy cle basis. the current sense comparator pwm latch configuration used ensures that only a single appears at the output during any given oscillator cycle. the i nductor curren t is converted to a voltageby inserting the ground referen ced sense resistor r s in series with the source of output switch q1. this voltage is monitored by the current sense input (pin 3) and compared to a level derived from the error amp output. the peak inductor current under normal operating cond itions is controlled by the voltage at pin 1 where: i pk = [v(pin 1) - 1.4v] / 3r s abnormal operating cond itions occur when the power supply output is overloaded or if output voltage sensing is lost, under these conditions, the current sense comparator threshold will be internally clamped to 1.0v. therefore the maximum peak swi tch current is: i pk (max) = 1.0v / r s when designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of r s to a reasonable level. a simple method to adjust this voltage is shown in figure 22. the two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. erratic operation due to noise pickup can result if there is an excessive redu ction of the i pk (max) clamp voltage. a narro w spike on the leading edge o f the current wav eform can usually be obs erved and may cause the po wer supply to exh ibit an instability when the output is lightly loaded. this spike is due to the power transformer interwinding capacitance and outpu t recti fier recovery time. the addition of an rc filter on the current sense i nput with a time constant that approximates the spike duration will usually eliminate the instability: refer to figure 26.
pj3843b high performance current mode controller 15-15 2002/01.ver.a millimet ers inch es dim min max min max a 9.07 9.32 0.357 0.367 b 6.22 6.48 0.245 0.255 c 3.18 4.43 0.125 0.135 d 0.35 0.55 0.019 0.020 g 2.54bsc 0.10bsc j 0.29 0.31 0.011 0.012 k 3.25 3.35 0.128 0.132 l 7.75 8.00 0.305 0.315 m - 10 - 10 millimet ers inches dim min max min max a 4.80 5.00 0.189 0.196 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27bsc 0.05bsc k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019

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